The invention relates to a local area network operating on the multiple bus system and with a plurality of interface modules connected between the multiple bus system and data-processing/generating subsystems.
Such a network is known from the publication of Ch. Steigner and K. Waldschmidt: "ASSCO--A Solution to Mutual Exclusion and Deadlock Situations in a Multiprocessor System", in the issue of H. W. Lawson, H. Berndt, G. Hermanson (eds): "Large Scale Integration", EUROMICRO 1978, North-Holland Publishing Company, pp. 82-92. FIG. 1 in this publication shows a diagram of a multiprocessor system, in which the interface modules connected between the multiple bus system and link subsystems (or processor modules) consist of bus switches controlled by the coordination system for the selection of one of the individual bus lines. A local area network thus configured has the disadvantage that only one of the bus switches can be activated at a time for each interface module, permitting only a single data flow between the respective processor module and the multiple bus system. In this way it is not possible to deliver any data at all to the multiple bus system during the data reception from the multiple bus system; this may present difficulties, especially with prolonged and/or frequent writing of new data into the processor-module memory.